| Description | The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew proble... |
| Features |
1
•2 5 – 43 MHz Support (140 Mbps to 1.2 Gbps Serial Link) • 4-Channel (3 data + 1 Clock) FPD-Link LVDS Outputs • 3 Low-Speed Over-Sampled LVCMOS Outputs • AC Coupled STP Interconnect up to 10 Meters in Length • Integrated Input Termination • @ Speed Link BIST Mode and Reporting Pin • Optional I2C Compatible Serial Control Bus • RGB666 + VS, HS, DE Converted from 1 Pair • Power Down Mode Minimizes Power Dissipation • FAST Random Data Lock; no Reference Clock Required • Adjustable Input Receive Equalization • LOCK (Real Time Link Status) Reporting Pin • Low EMI FPD-Link Output • SSCG Option for... |
| Datasheet |
 DS99R124Q Datasheet - 0.98MB |
| Part Number | Description |
|---|---|
 Texas Instruments |
5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data... |
 National Semiconductor |
5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS99R124Q converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data s... |