| Description | www.ti.com PACKAGE OPTION ADDENDUM 4-Dec-2021 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) JM38510/30109BEA JM38510/30109BFA JM38510/30109BFA M38510/30109BEA M38510/30109BEA M38510/30109BFA M38510/30109BFA SN54LS109AJ SN54LS109... |
| Features |
0 RoHS & Green
D
16 2500 RoHS & Green
N
16
25 RoHS & Green
N
16
25 RoHS & Green
N
16
25 RoHS & Green
Lead finish/ Ball material
(6)
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
MSL Peak Temp Op Temp (°C)
(3)
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
Level-1-260C-UNLIM Level-1-260C-UNLIM...
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| Datasheet |
 74109 Datasheet - 921.96KB |
| Part Number | Description |
|---|---|
 National Semiconductor |
Triple 3 Input NAND Gates This device contains three independent gates each of which performs the logic NAND function Features Y Alternate Military Aerospace device (5410) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6500 – 1 Order Number 5410DMQB 5410FMQB DM5410J DM5410W or DM7410N See NS Package Number J14A N14A or W14B Function Table Y e ABC Inputs Output ABC Y XXL XLX LXX HHH H H H L H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level C1995 National Semiconductor Corporation TL F 6500 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices ... |
 Philips |
Triple 3-input NAND gate The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS tPHL/ tPLH CI CPD propagation delay nA, nB, nC to nY input capacitance power dissipation capacitance per gate CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply volta... |
 STMicroelectronics |
DUAL J-K FLIP-FLOP The M54/74HC107 is a high speed CMOS DUAL JK FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74H... |
 Fairchild Semiconductor |
Triple 3 Input AND Gate ... |
 ETC |
TRIPLE 3-INPUT AND Vcc 14 13 12 11 10 9 8 1 2 3 4 5 6 7 GND 7411: TRIPLE 3-INPUT AND ... |
STMicroelectronics |
DUAL J-K FLIP FLOP The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection ... |
Fairchild Semiconductor |
Triple 3-Input NAND Gate ... |
Fairchild Semiconductor |
Monostable multivibrator The DM74121 is a monostable multivibrator featuring both positive and negative edge triggering with complementary outputs. An internal 2kΩ timing resistor is provided for design convenience minimizing component count and layout problems. this device can be used with a single external capacitor. Inputs (A) are active-LOW trigger transition inputs and input (B) is and active-HIGH transition Schmitttrigger input that allows jitter-free triggering from inputs with transition rates as slow as 1 volt/second. A high immunity to VCC noise of typically 1.5V is also provided by internal circuitry at the input stage. To obtain optimum and trouble free operation please read operating rules and one-shot ... |
 Texas Instruments |
Retriggerable Monostable Multivibrators SN54122, SN54123, SN54130, SN54LS122, SN54LS123, SN74122, SN74123, SN74130, SN74LS122, SN74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS SDLS043 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 SN54122, SN54123, SN54130, SN54LS122, SN54LS123, SN74122, SN74123, SN74130, SN74LS122, SN74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS SDLS043 – DECEMBER 1983 – REVISED MARCH 1988 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN541... |
ETC |
RETRIGGERABLE MONOSTABLE MULTIVIBRATOR www.DataSheet4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataSheet4U.com DataSheet4U.com DataSheet4U.com DataSheet 4 U .com ... |
Texas Instruments |
Retriggerable Monostable Multivibrators SN54122, SN54123, SN54130, SN54LS122, SN54LS123, SN74122, SN74123, SN74130, SN74LS122, SN74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS SDLS043 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 SN54122, SN54123, SN54130, SN54LS122, SN54LS123, SN74122, SN74123, SN74130, SN74LS122, SN74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS SDLS043 – DECEMBER 1983 – REVISED MARCH 1988 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN541... |
Fairchild Semiconductor |
Dual retriggerable monostable multivibrator ... |
Fairchild Semiconductor |
Quad 3-STATE Buffer This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order N... |
National Semiconductor |
Quad Bus Buffer Gate ... |
Texas Instruments |
QUADRUPLE BUS BUFFERS These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors. When disabled, both output transistors are turned off, presenting a high-impedance state to the bus so the output will act neither as a significant load nor as a driver. The ’125 and ’LS125A devices’ outputs are disabled when G is high. The ’126 and ’LS126A devices’ outputs are disabled when G is low. SN54125, SN54126, SN54LS125A, SN54LS126A . . . J OR W PACKAGE SN74125, SN74126 . . . N PACKAGE SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE... |
Fairchild Semiconductor |
Quad 3-STATE Buffer This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order N... |