| Description | The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables. Includes Hitless Switching and ... |
| Features |
◆ Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-12 ◆ Similar to the M2006-02A - and pin-compatible - but adds Hitless Switching and Phase Build-out functions ◆ Includes APC pin for Phase Build-out function (for absorption of the input phase change) ◆ Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation ◆ Input reference and VCSO frequencies up to 700MHz (Specify VCSO frequency at time of order) ◆ Low phase jitter of 0.25 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ Commercial and Industrial temperature grades ◆...
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| Datasheet |
 M2006-12A Datasheet - 419.09KB |
| Part Number | Description |
|---|---|
 Integrated Circuit Solution Inc |
VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when th... |