| Description | The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming ... |
| Features |
• Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including: • 255/238 (OTU1) Mapping and 238/255 De-mapping • 255/237 (OTU2) Mapping and 237/255 De-mapping • 255/236 (OTU3) Mapping and 236/255 De-mapping Example I/O Clock Frequency Combinations Using M2006-02/-12-622.0800 and Inverse FEC Ratios FEC PLL Ratio Mfec / Rfec 1/1 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 672.1627 Output Clock (either output) MHz 622.08 or 155.52 • Supports input reference and VCSO frequencies up • • • • • to 700MHz, supports loop timing modes (... |
| Datasheet |
 M2006-02 Datasheet - 83.76KB |
| Part Number | Description |
|---|---|
 Integrated Circuit Solution Inc |
VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when th... |
 Integrated Circuit Systems |
VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables. Includes Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz. ... |